Aligners have been used when terminating a synchronous multiplex, such as a framed 2048 kbit/s link, onto a functional unit, where the clock of the functional unit and the clock of the synchronous multiplex cannot be assumed to be of the same frequency and phase.
The use of aligners implies a synchronous service which will tolerate (although reluctantly) some slips. The design characteristic of an aligner is that if the limit of its buffering is reached then a controlled slip is performed. For a framed multiplex the slips usually equate to a frame of data, in which case the aligner is often referred to as a frame aligner. Aligners not only must be able to accept any phase of the incoming stream, but also must include sufficient hysteresis to cope with delay variations introduced by the network.
The use of frame aligners can also be extended to the termination of a framed multiplex carried in a Virtual Container by a Synchronous Digital Hierarchy (SDH) multiplex or the termination of a framed multiplex carried in a cell based Virtual Circuit by an Asynchronous Transfer Mode (ATM) multiplex, so that traffic of a nominal constant bit rate can be transferred from such multiplexes onto functional units which are expecting traffic of the same nominal constant bit rate. Such a functional unit could be a synchronous switch, or a digital to analogue to decoder, or in the case of ATM an asynchronous to synchronous adaptation function.
SDH traffic is characterised by being packed into columns with a percentage of stuffing. Asynchronous traffic is characterised by being carried in packets, frames or cells, cells being the term used commonly for ATM traffic. ATM cells are of a constant size and can carry a fixed amount of constant bit rate (CBR) traffic data.
When an aligner slips it must miss out a fixed amount of data if the traffic is arriving too quickly. If the traffic is arriving too slowly, then either a fixed amount of data is repeated or a fixed substitution set of data is inserted.
An example of a frame alignment detector was disclosed in Patent Number GB 2262417B, corresponding to U.S. Pat. No. 5,377,209.
Examples of frame aligners were disclosed in Patent Numbers GB 2063624A and GB 2151437A corresponding to U.S. Pat. No. 4,368,531 and U.S. Pat. No. 4,617,659 respectively. The aligner for the present application will require similar overall functional characteristics, but the hysteresis range will have to be substantially greater, perhaps in excess of a millisecond. The aligner also needs to have a slip limit adjusted when no cells have been received for some time and then to reject fill-in cells until frame alignment has been recovered.
Protocols for High-Speed Networks IIxe2x80x94Proceedings of the IFIG WG 6.1, WG 6.4 Second International Workshopxe2x80x94Nov. 29, 1990, Palo Alto, USA, Pages 353-367 xe2x80x9cA Proposed Segmentation and Re-Assembly (SAR) Protocol for Use with Asynchronous Transfer Mode (ATM)xe2x80x9d describes where segmentation and reassembly of protocol data units into and from fixed-size cells in an Asynchronous Transfer Mode network is carried out by the Adaptation Layer of the network using Segmentation and Reassembly protocols. An experimental Segmentation and Reassembly protocol has been developed to be used with all desired Asynchronous Transfer mode services. The use of a single protocol for all services simplifies implementation and interoperability. Among its main characteristics, the protocol provides cell-based error correction and detection, a cell sequence number modulo 1024 to provide cell sequence integrity, and the ability for applications to insert control cells in the Asynchronous Transfer Mode cell stream.
According to the present invention there is provided where an Asynchronous Transfer Mode (ATM) multiplexed data stream is terminated at a functional unit, the virtual channel data being carried in cells in the data stream, a depacketiser comprising a plurality of cell buffers, each buffer storing the payload data contained in a single cell, the buffers being loaded in sequence in accordance with a message sequence number carried by each cell and emptied in accordance with a depacketiser algorithm to form a non-continuous data stream; a fill-in cell format generator which on the failure of a valid cell to arrive causes the replacement of the missing cell by a fill-in cell in the non-continuous data stream; a time-out function generator which is started after each cell has been depacketised and also after fill-in replacement cells have been generated except when the cell buffers have at least two full cells and at least two fill-in cells have been generated in succession.
There is also provided a cell frame aligner comprising a depacketiser as above and further comprising a frame alignment signal detector which detects a frame alignment signal in the non-continuous data stream and generates an associated frame start signal and a loss of frame alignment signal as appropriate; and a frame aligner which accepts the non-continuous data stream and its associated frame start signal, except in the presence of a loss of frame alignment signal, and aligns the non-continuous data stream to clock and frame start signals of the functional unit.
The algorithm which is used following the depacketisation of cell (n), or the generation of a fill-in cell to replace a missing cell (n), to determine when to depacketise the next cell buffer, or to supply a fill-in cell may be as follows: cell (n+1) is depacketised and the time-out cleared and restartedxe2x80x94if cell buffers (n+1) and (n+2) are full,xe2x80x94or if cell (n+1) is full and the time-out has matured,xe2x80x94or if cell (n+1) is full, the time-out has not matured and a fill-in cell has just been completed which cleared and restarted the time-out; cell (n+1) is replaced by a fill-in cell and the time-out is neither cleared nor restarted if cell buffer (n+1) is empty and there are at least 2 full cell buffers; cell (n+1) is replaced by a fill-in cell and the time-out is cleared and restarted if cell buffer (n+1) is empty, the time-out has matured and there is only one full cell buffer; if none of the preceding sets of conditions apply then no action is taken until one of them does apply.
The algorithm used to determine when to depacketise a full cell buffer, or to supply a fill-in cell to replace a missing cell, or to just wait is as follows:
When cell (n) has been emptied and the full/empty binary flat has been set to empty or the fill-in cell generator has completed the generation of a fill-in cell to replace a missing cell (n), then if one of the following sets of conditions applies then the specified action is taken: if one of the following sets of conditions does not apply then no action is taken until one of them does apply:
A If cell buffer (n+1) is full and cell buffer (n+2) is full: then the contents of the cell (n+1) are passed to the frame alignment signal detector and the aligner; and the time-out is cleared and restarted.
B If cell buffer (n+1) is full, cell buffer (n+2) is empty and the time-out has matured: then the contents of the cell (n+1) are passed to the frame alignment signal detector and the aligner; and the time-out is cleared and restarted.
C If cell buffer (n+1) is full, cell buffer (n+2) is empty, the time-out has not matured and the last condition cycle was a fill-in cell generated as a result of conditions for E applying: then the contents of the cell (n+1) are passed to the frame alignment signal detector and the aligner; and the time-out is cleared and restarted.
D If cell buffer (n+1) is empty and the depacketiser has at least 2 full cell buffers: then the cell (n+1) is declared as missing; the fill-in cell generator generates a fill-in cell which is passed to the frame alignment signal detector and the aligner; and the time-out is neither cleared nor restarted.
E It cell buffer (n+1) is empty, the time-out has matured and there is only one full cell buffer in the depacketiser: then the cell (n+1) is declared as missing; the fill-in cell generator generates a fill-in cell which is passed to the frame alignment signal detector and the aligner; and the time-out is cleared and restarted.
Because a byte of ATM data does not necessarily correspond to a time slot of a 2048 kbit/s framed multiplex, it is appropriate to pass the data from the depacketiser to the aligner and frame alignment signal detector as a clocked serial data stream, where the clock is not continuous, but a burst of 376 clock pulses and is followed by a variable length pause.